1. Field of Invention
This invention relates to semiconductor processing and in particular to fabricating ESD protection devices in a silicided CMOS process.
2. Description of Related Art
With the increase in the level of integration of semiconductor product device structures have shrunk leaving less volume of material to dissipate heating from current surges caused by electrostatic discharge (ESD). Making input and output devices large enough to dissipate the energy from an ESD uses valuable semiconductor real estate. Various attempts have been made to lengthen the path of the discharge current keeping the transistor devices small and providing a way to absorb the ESD energy.
In U.S. Pat. No. 5,733,794 (Gilbert et al.) an ESD protection transistor has a halo region of opposite conductivity from the source and drain. The halo region permits the ESD protection transistor to have a breakdown voltage adjusted so as to turn on before the device being protected is affected by an ESD. In U.S. Pat. No. 5,721,439 (Lin) is described an ESD protection transistor with a drain having a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands providing uniform resistance of the drain suitable for providing ESD protection. In U.S. Pat. No. 5,719,733 (Wei et al.) a device for ESD protection uses a silicon controlled rectifier configuration with controllable triggering voltage, The ESD protection device is connected between ground and the I/O pin of the circuit to be protected.
In U.S. Pat. No. 5,629,544 (Voldman et al.) a diode in a well with a trench isolation is used for ESD protection. Both the well diode contacts are silicided and a gate structure is used to space the diode contact for the trench isolation edge. In U.S. Pat. No. 5,477,413 (Watt) an ESD protection circuitry is constructed in a P-well using a P-well with a diode for negative ESD voltages and a P-well with a multiple FET's for positive ESD voltages. Circuits for both the positive and negative ESD voltages connect the resulting current from an ESD event into a metal conduit. In U.S. Pat. No. 5,446,302(Beigel et al.) In U.S. Pat. No. 5,446,302 (Beigel et al.) a diode connected bipolar transistor device is disclosed that provides protection from ESD. The device functions as a transistor in the active region an ESD event with the current path from collector to emitter and lowering the ESD current density. In U.S. Pat. No. 5,440,162 (Worley et al.) an ESD protection circuit for pads of an integrated circuit using silicide-clad diffusions is described. The circuit uses a robust N+diode with an N-well block, an NFET and a transient clamp, each with a distributed N-well drain resistor to prevent avalanching and leakage. In U.S. Pat. No. 5,272,097 (Shiota) a process is described for forming diodes in a process which simultaneously forms MOS or CMOS devices. The diodes have a relatively low breakdown voltage, making them suitable for ESD protection devices. In U.S. Pat. No. 5,021,853 (Mistry) an ESD protection device is formed by an N-channel grounded gate transistor. The protection device has a polysilicon gate but there is no silicide on top of the gate or on the drain and source near the gate to minimize adverse effects of ESD events.
During an electrostatic discharge heating takes place in the area of the drain. This is a result of a junction breakdown at the drain junction which allows a large amount of current to flow. If the current is not spread out across a sufficiently large volume, the resulting heat will not be dissipated and damage to the device will result. As semiconductor devices are shrunk and integrated together in larger and larger quantities, the sensitivity to ESD becomes worse. A way is described in this invention allow small devices, permitting adequate dissipation of heat from an electrostatic discharge and reducing by one the number of masks required over prior art.